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Serial peripheral interface (SPI)
RM0008
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F S = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
F S = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
When the master clock is disabled (MCKOE bit cleared):
F S = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
F S = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
Table 166 and Table 167 provide example precision values for different clock configurations.
Note:
Other configurations are possible that allow optimum clock precision.
Table 166. Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line
devices only)
PREDIV2 PLL3 I2SDIV I2SODD
16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit
MCLK
Target
F S (Hz)
Real F S (kHz)
16-bit 32-bit
Error
16-bit 32-bit
6
7
8
11
8
7
8
9
4
13
5
5
5
9
8
4
6
12
8
4
8
11
8
9
4
13
5
5
5
9
8
4
14
20
14
16
14
20
14
20
8
16
9
9
13
14
14
10
14
14
14
10
14
16
14
20
8
16
9
9
13
14
14
10
19
46
31
35
62
139
124
217
2
2
4
5
11
9
15
30
9
9
15
30
31
35
62
108
2
2
4
5
11
9
15
30
0
1
0
1
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
96000
48000
44100
32000
22050
16000
11025
8000
96000
48000
44100
32000
22050
16000
11025
8000
95942.98 95942.98 0.0594% 0.0594%
48003.07 47971.49 0.0064% 0.0594%
44102.82 44102.82 0.0064% 0.0064%
32010.24 32018.44 0.0320% 0.0576%
22051.41 22051.41 0.0064% 0.0064%
16001.02 16005.12 0.0064% 0.0320%
11025.71 11025.71 0.0064% 0.0064%
8000.512 8000.512 0.0064% 0.0064%
97656.25 97656.25 1.7253% 1.7253%
48076.92 48076.92 0.1603% 0.1603%
43945.31 43945.31 0.3508% 0.3508%
31960.22 31960.22 0.1243% 0.1243%
22078.80 22078.80 0.1306% 0.1306%
15990.49 15990.49 0.0594% 0.0594%
11025.70 11025.70 0.0064% 0.0064%
8004.611 8004.611 0.0576% 0.0576%
608/995
Doc ID 13902 Rev 9
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